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M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 the samsung M366S3323DTU is a 32m bit x 64 synchronous dynamic ram high density memory module. the samsung M366S3323DTU consists of sixteen cmos 16m x 8 bit with 4banks synchronous drams in tsop-ii 400mil package and a 2k eeprom in 8-pin tssop package on a 168-pin glass-epoxy substrate. two 0.1uf decoupling capacitors are mounted on the printed circuit board in parallel for each sdram and four 2.2uf bulk capacitors per dimm. the M366S3323DTU is a dual in-line memory module and is intended for mounting into 168-pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. ? performance range ? burst mode operation ? auto & self refresh capability (4096 cycles/64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs latency (access from column address) burst length (1, 2, 4, 8 & full page) data scramble (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? serial presence detect with eeprom ? pcb : height (1,125mil) , double sided component part no. max freq. (speed) M366S3323DTU- c /l7c 133mhz (7.5ns @ cl=2) M366S3323DTU-c/l7a 133mhz (7.5ns @ cl=3) M366S3323DTU- c /l 1 h 100mhz (10ns @ cl=2) M366S3323DTU-c/l 1 l 100mhz (10ns @ cl=3) feature general description M366S3323DTU sdram dimm 32mx64 sdram dimm based on 16mx8, 4banks, 4k refresh, 3.3v synchronous drams with spd pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin name function a0 ~ a11 address input (multiplexed) ba0 ~ ba1 select bank dq0 ~ dq63 data input/output clk0 ~ clk3 clock input cke0 ~ cke1 clock enable input cs0 ~ cs3 chip select input ras row address strobe cas column address strobe we write enable dqm0 ~ 7 dqm v dd power supply (3.3v) v ss ground *v ref power supply for reference sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom du don t use nc no connection pin configurations (front side/back side) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 front v ss dq0 dq1 dq2 dq3 v dd dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 v dd dq14 dq15 *cb0 *cb1 v ss nc nc v dd we dqm0 pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 front dqm1 cs0 du v ss a0 a2 a4 a6 a8 a10/ap ba1 v dd v dd clk0 v ss du cs2 dqm2 dqm3 du v dd nc nc *cb2 *cb3 v ss dq16 dq17 pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 front dq18 dq19 v dd dq20 nc *v ref cke1 v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 v dd dq28 dq29 dq30 dq31 v ss clk2 nc nc **sda **scl v dd pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 back v ss dq32 dq33 dq34 dq35 v dd dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 v dd dq46 dq47 *cb4 *cb5 v ss nc nc v dd cas dqm4 pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 back dqm5 cs1 ras v ss a1 a3 a5 a7 a9 ba0 a11 v dd clk1 *a12 v ss cke0 cs3 dqm6 dqm7 *a13 v dd nc nc *cb6 *cb7 v ss dq48 dq49 pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 back dq50 dq51 v dd dq52 nc *v ref nc v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 v dd dq60 dq61 dq62 dq63 v ss clk3 nc **sa0 **sa1 **sa2 v dd samsung electronics co., ltd. reserves the right to change products and specifications without notice.
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 pin configuration description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+t ss prior to valid command. a0 ~ a11 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra11, column address : ca0 ~ ca9 ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm0 ~ 7 data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic.
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 functional block diagram a0 ~ an, ba0 & 1 cke0 ras cas we sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u7 10 w dqn every dqpin of sdram dqm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs cs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm cs dqm1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm cs dqm5 dqm4 dqm2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqm cs cs2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm cs dqm3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm cs dqm7 dqm6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u8 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u9 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u10 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u11 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u12 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u13 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u14 dqm cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u15 dqm cs cs1 cs3 cke1 sdram u8 ~ u15 10k w v dd v dd vss two 0.1uf capacitors per each sdram to all sdrams serial pd sda scl a1 a2 a0 sa1 sa2 sa0 wp 47k w u0/u9/u4/u12 u5/u14/u8/u16 10 w clk0/1/2/3 u2/u10/u3/u13 u1/u15/u7/u17 3.3 pf *1 u6/u11 *1 : for 4 loads, clk2 & clk3 only.
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 16 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions and characteristics capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref = 1.4v 200 mv) pin symbol min max unit address (a0 ~ a11, ba0 ~ ba1) ras , cas , we cke (cke0 ~ cke1) clock (clk0 ~ clk3) cs ( cs0 ~ cs3 ) dqm (dqm0 ~ dqm7) dq (dq0 ~ dq63) c add c in c cke c clk c cs c dqm c out 45 45 25 15 15 10 13 85 85 45 21 25 15 18 pf pf pf pf pf pf pf recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes :
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noted, input swing level is cmos(v ih /v il =v ddq /v ssq ) notes : dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note - 7c -7a -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 1040 960 960 960 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 32 ma i cc2 ps cke & clk v il (max), t cc = 32 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 320 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 160 active standby current in power-down mode i cc3 p cke v il (max), t cc = 10ns 80 ma i cc3 ps cke & clk v il (max), t cc = 80 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 10ns input signals are changed one time during 20ns 480 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 400 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 1120 1120 1040 1040 ma 1 refresh current i cc5 t rc 3 t rc (min) 2000 1840 1760 1760 ma 2 self refresh current i cc6 cke 0.2v c 32 ma l 12.8
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter notes : (ac operating conditions unless otherwise noted) parameter symbol version unit note - 7c - 7a - 1h -1l row active to row active delay t rrd (min) 15 15 20 20 ns 1 ras to cas delay t rcd (min) 15 20 20 20 ns 1 row precharge time t rp (min) 15 20 20 20 ns 1 row active time t ras (min) 45 45 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 60 65 70 70 ns 1 last data in to row precharge t rdl (min) 2 clk 2,5 last data in to active delay t dal (min) 2 clk + trp - 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. in 100mhz and below 100mhz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. samsung recommends trdl=2clk and tdal=2clk + trp.
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol - 7c - 7a - 1h - 1l unit note min max min max min max min max clk cycle time cas latency=3 t cc 7.5 1000 7.5 1000 10 1000 10 1000 ns 1 cas latency=2 7.5 10 10 12 clk to valid output delay cas latency=3 t sac 5.4 5.4 6 6 ns 1,2 cas latency=2 5.4 6 6 7 output data hold time cas latency=3 t oh 3 3 3 3 ns 2 cas latency=2 3 3 3 3 clk high pulse width t ch 2.5 2.5 3 3 ns 3 clk low pulse width t cl 2.5 2.5 3 3 ns 3 input setup time t ss 1.5 1.5 2 2 ns 3 input hold time t sh 0.8 0.8 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 5.4 6 6 ns cas latency=2 5.4 6 6 7 refer to the individual componenet, not the whole module.
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clock cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes : x
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 package dimensions 0.150 max 0.050 0.0039 (1.270 0.10) 0.250 (6.350 ) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350 ) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0 .100) 0.079 0.004 (2.000 0.100) 0 . 1 6 5 m i n ( 4 . 1 9 m i n ) (3.81 max) tolerances : .005(.13) unless otherwise specified the used device is 16mx8 sdram, tsop sdram part no. : k4s280832d 5.250 5.014 units : inches (millimeters) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0 . 1 1 8 ( 3 . 0 0 0 ) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) .118dia 0.004 (3.000dia 0.100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) (127.350) (133.350) 1 . 1 2 5 ( 2 8 . 5 7 5 ) 0.118 (3.000) 0.050 0.039 0.002 0.008 0.006 (0.200 0.150) (1.000 0. 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 M366S3323DTU-l7c/l7a/l1h/l1l ,c7c/c7a/c1h/c1l (intel spd 1.2b ver. base) byte # function described function supported hex value note -7c -7a -1h -1l -7c -7a -1h -1l 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram 04h 3 # of row address on this assembly 12 0ch 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 2 row 02h 6 data width of this assembly 64 bits 40h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time @cas latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h a0h a0h 2 10 sdram access time from clock @cas latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2 11 dimm configuraion type non parity 00h 12 refresh rate & type 15.625us, support self refresh 80h 13 primary sdram width x8 08h 14 error checking sdram width none 00h 15 minimum clock delay for back-to-back random column address t ccd = 1clk 01h 16 sdram device attributes : burst lengths supported 1, 2, 4, 8 & full page 8fh 17 sdram device attributes : # of banks on sdram device 4 banks 04h 18 sdram device attributes : cas latency 2 & 3 2 & 3 2 & 3 2 & 3 06h 06h 06h 06h 19 sdram device attributes : cs latency 0 clk 01h 20 sdram device attributes : write latency 0 clk 01h 21 sdram module attributes non-buffered, non-registered & redundant addressing 00h 22 sdram device attributes : general +/- 10% voltage tolerance, burst read single bit write precharge all, auto precharge 0eh 23 sdram cycle time @cas latency of 2 7.5ns 10ns 10ns 12ns 75h a0h a0h c0h 2 24 sdram access time from clock @cas latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2 25 sdram cycle time @cas latency of 1 - 00h 26 sdram access time from clock @cas latency of 1 - 00h 27 minimum row precharge time (=t rp ) 15ns 20ns 20ns 20ns 0fh 14h 14h 14h 28 minimum row active to row active delay (t rrd ) 15ns 15ns 20ns 20ns 0fh 0fh 14h 14h 29 minimum ras to cas delay (=t rcd ) 15ns 20ns 20ns 20ns 0fh 14h 14h 14h 30 minimum activate precharge time (=t ras ) 45ns 45ns 50ns 50ns 2dh 2dh 32h 32h 31 module row density 2 row of 128mb 20h 32 command and address signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 33 command and address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h organization : 32mx64 composition : 16mx8 *16 used component part # : k4s280832d-tl7c/tl75/tl1h/tl1l,tc7c/tc75/tc1h/tc1l # of rows in module : 2 row # of banks in component : 4 banks feature : 1,125mil height & single sided component refresh : 4k/64ms contents ;
M366S3323DTU pc133/pc100 low profile unbuffered dimm rev. 0.1 sept. 2001 byte # function described function supported hex value note -7c -7a -1h -1l -7c -7a -1h -1l 35 data signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 36~61 superset information (maybe used in future) - 00h 62 spd data revision code intel rev 1.2b 12h 63 checksum for bytes 0 ~ 62 - 6fh b0h 17h 47h 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuration) 3 33h 75 manufacturer part # (data bits) blank 20h 76 ...... manufacturer part # (data bits) 6 36h 77 ...... manufacturer part # (data bits) 6 36h 78 manufacturer part # (mode & operating voltage) s 53h 79 manufacturer part # (module depth) 3 33h 80 ...... manufacturer part # (module depth) 3 33h 81 manufacturer part # (refresh, #of banks in comp. & interface) 2 32h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) d 44h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision & type) u 55h 86 manufacturer part # (hyphen) " - " 2dh 87 manufacturer part # (power) l/c 4ch/43h 88 manufacturer part # (minimum cycle time) 7 7 1 1 37h 37h 31h 31h 89 manufacturer part # (minimum cycle time) c a h l 43h 41h 48h 4ch 90 manufacturer part # (tbd) blank 20h 91 manufacturer revision code (for pcb) u 55h 92 ...... manufacturer revision code (for component) d-die (5th gen.) 44h 93 manufacturing date (year) - - 3 94 manufacturing date (week) - - 3 95~98 assembly serial # - - 4 99~125 manufacturer specific data (may be used in future) undefined - 126 system frequency for 100mhz 100mhz 64h 127 pc100 specification details detailed pc100 information ffh ffh ffh fdh 128+ unused storage locations undefined - 1. the row select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. note :

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